Intel CEO Lip-Bu Tan has a blunt new chip rule for engineers: You’re fired if you don’t get…

Intel CEO Lip-Bu Tan has issued a blunt ultimatum to his engineers: deliver chips that work on the first tape-out, or face the sack. Speaking at JP Morgan's tech conference, Tan said A0 silicon must go straight to production, B0 is tolerated, anything beyond gets you fired. The Intel CEO, who also told CNBC's Jim Cramer he scrapped reporting silos, is rewriting the chipmaker's design culture to chase TSMC.

Intel CEO Lip-Bu Tan has put a hard line under his engineering teams: get a chip right on the first tape-out, or start looking for another job. Speaking at JP Morgan's Global Technology, Media and Communications Conference, Tan said he has rewired Intel's design culture to demand A0 silicon that goes straight to production, a discipline the company has historically struggled to enforce.

"A0 is when you tape out, first time pass," Tan said. Intel hasn't had that culture, he added. "B0, you keep your job. Anything above that, you are fired."

The warning is not theoretical. Intel's Xeon "Sapphire Rapids" famously needed a dozen steppings, from A0 all the way to E5, to clear roughly 500 bugs before shipping. Tan wants that era buried.

From Sapphire Rapids' 500-bug saga to a one-shot tape-out mandate

Engineers initially thought Tan was joking. He says they don't anymore. He now personally reviews chip designs and the IP blocks going into them before tape-out, pushing teams toward heavier pre-silicon verification and less ambitious design swings to avoid costly respins. Nvidia bakes in redundant logic and caches to dodge stepping failures. Intel's approach has historically been different, and that's the gap Tan wants closed.

The culture shift is part of a wider cleanup. In a separate sit-down with CNBC's Jim Cramer on Mad Money, Tan admitted Intel "used to have leadership in data center, and over the years we lost it." Server market share has slid to 72% as of Q3 2025, down from 91% in early 2019, with AMD eating most of the difference.

Engineering now reports straight to the CEO as Intel chases TSMC on 14A

Tan told Cramer that from day one he had every engineering team report directly to him, scrapping what he called "too many silos, too many people reporting." He has also brought back former Intel employees for specific product lines. 18A yields, meanwhile, are now improving 7% to 8% per month, which Tan calls the industry best-practice rate.

The roadmap is moving too. Intel's 14A node is on track for risk production in 2028 and volume in 2029, lining up with TSMC's A14. Tan also confirmed 10A and 7A are in active planning, while the 14A PDK 0.9, which he calls the "Holy Grail," lands for external customers in October 2026. Apple has signed on for 18A, with Elon Musk's TeraFab lined up for 14A. The message to staff is the same as the one to customers: hit the date, hit the spec, or you're out.