Explained: What is Huawei's LogicFolding, Tau Scaling Law, and how it plans to build 1.4nm chips without ASML

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Huawei has unveiled the Tau (τ) Scaling Law and a new LogicFolding chip architecture, aiming to build 1.4nm-class chips by 2031 without ASML's EUV lithography machines. Announced by chip chief He Tingbo at IEEE ISCAS 2026 in Shanghai, the design stacks logic circuits to boost transistor density by 55% and power efficiency by 41%. The tech debuts in Huawei's Kirin processor for the Mate 90 series this autumn, challenging Moore's Law and US sanctions.

Huawei says it has worked out how to build 1.4nm-class chips by 2031 without ever touching ASML's most advanced lithography machines. Chip chief He Tingbo, who also chairs Huawei's Scientist Committee, unveiled the plan on Monday at the IEEE ISCAS 2026 symposium in Shanghai, branding it the Tau (τ) Scaling Law. Internally, Huawei is also calling it "Her's Law," a nod to its semiconductor head.

The architecture that puts the theory into silicon is called LogicFolding. Huawei is claiming a 55% jump in transistor density and a 41% gain in power efficiency. It will debut later this year in the Kirin processor expected to power the Mate 90 series.

Moore's Law shrinks transistors. Tau Scaling shrinks time.

For five decades, chipmakers chased Moore's Law by cramming smaller transistors onto silicon. That cadence has been slowing across the industry. For Huawei, it stopped entirely. He Tingbo said Huawei's scaling efforts plateaued six years ago, right after US sanctions cut off access to extreme ultraviolet lithography.

The new pitch is to stop shrinking parts and start shrinking the time signals take to move between them. That's what the Greek letter τ stands for in chip design—propagation delay. Reduce τ across devices, circuits, chips, and systems, the argument goes, and you can wring frontier-class performance out of older equipment. He Tingbo called the approach "feasible and affordable," and promised "a big leap ahead" rather than another safe upgrade.

LogicFolding: stacking circuits to cut the wires short

LogicFolding is the physical execution. It folds logic circuits into two stacked layers so signals don't have to travel as far, slashing the resistive and capacitive load that slows them down. Huawei is pairing it with a new system-level interconnect called UnifiedBus, designed to cut communication latency between chips inside a SuperPoD.

The company says it has already mass-produced 381 chips over six years using related techniques, across smartphones and AI computing. None of those numbers have been independently verified.

The catch: density equivalent, not a true 1.4nm node

Here's the caveat the press release doesn't lead with. Huawei isn't claiming it will fab a true 1.4nm transistor. It's claiming density equivalent to a 1.4nm process, achieved by stacking and packing rather than by shrinking. Modern node labels are already marketing more than measurement, but the distinction matters when stacked against TSMC's A14 node, which is on track for mass production in 2028, three years ahead of Huawei's target.

Why it matters in the US-China chip war

If LogicFolding holds up at scale, it dents an industry assumption that EUV is non-negotiable below 5nm. SMIC shares jumped more than 19% in Shanghai on the news. Huawei plans to extend the architecture to its Ascend AI accelerators and data centre clusters by 2030, where the real prize sits—a homegrown alternative to the Nvidia hardware Beijing can no longer buy.

TSMC still gets to 1.4nm first. Huawei's bet is that arriving second on its own road beats waiting indefinitely on someone else's.